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1/66 january 2002 n high performance cpu C 16-bit cpu with 4-stage pipeline C 80ns instruction cycle time @ 25mhz clk C 400ns 16 x 16-bit multiplication C 800ns 32 / 16-bit division C enhanced boolean bit manipulation facilities C additional instructions to support hll and operating systems C single-cycle context switching support n memory organization C 32k byte on-chip rom memory C up to 16m byte linear address space for code and data (5m byte with can) C 2k byte on-chip internal ram (iram) C 2k byte on-chip extension ram (xram) n fast and flexible bus C programmable external bus characteristics for different address ranges C 8-bit or 16-bit external data bus C multiplexed or demultiplexed external address/data buses C five programmable chip-select signals C hold-acknowledge bus arbitration support n interrupt C 8-channel peripheral event controller for single cycle, interrupt driven data transfer C 16-priority-level interrupt system with 56 sources, sample-rate down to 40ns n timers C two multi-functional general purpose timer units with 5 timers C two 16-channel capture/compare units n a/d converter C 16-channel 10-bit C 7.76 m s conversion time n fail-safe protection C programmable watchdog timer C oscillator watchdog n on-chip can 2.0b interface n on-chip bootstrap loader n clock generation C on-chip pll C direct or prescaled clock input n up to 111 general purpose i/o lines C individually programmable as input, output or special function C programmable drive strength C programmable threshold (hysteresis) n idle and power down modes C idle current <95ma C power-down supply current <400 m a n 4-channel pwm unit n serial channels C synchronous/async serial channel C high-speed synchronous channel n development support C c-compilers, macro-assembler packag- es, emulators, eval boards, hll-debug- gers, simulators, logic analyzer disassemblers, programming boards n 144-pin pqfp package pqfp144 (28 x 28 mm) (plastic quad flat pack) port 0 port 1 port 4 port 6 port 5 port 3 port 2 gpt1 gpt2 asc usart brg 32k cpu-core internal ram watchdog interrupt controller 8 8 15 16 32 16 pec 16 16 can port 7 port 8 external bus 10-bit adc brg ssc pwm capcom2 capcom1 8 16 16 osc. xram 16 controller 16 8 16 byte rom st10c167 16-bit mcu with 32k byte rom this is advance information on a new product now in development or undergoing evaluation. details are subject to change without notice.
st10c167 2/66 table of contents page 1 introduction ......................................................................................................... 4 2 pin data .................................................................................................................. 5 3 functional description.................................................................................... 10 4 memory organization........................................................................................ 11 5 central processing unit (cpu) ...................................................................... 12 6 external bus controller............................................................................... 13 7 interrupt system ................................................................................................ 14 8 capture/compare (capcom) unit ................................................................... 17 9 general purpose timer unit ........................................................................... 18 9.1 gpt1 ...................................................................................................................... .... 18 9.2 gpt2 ...................................................................................................................... .... 19 10 pwm module ........................................................................................................... 21 11 parallel ports .................................................................................................... 22 12 a/d converter....................................................................................................... 23 13 serial channels .................................................................................................. 24 14 can module ............................................................................................................ 26 15 watchdog timer................................................................................................... 26 16 instruction set summary ................................................................................ 27 17 system reset ......................................................................................................... 29 18 power reduction modes .................................................................................. 30 19 special function register overview.......................................................... 31 19.1 identification registers ................................................................................. 37 20 electrical characteristics .......................................................................... 38 20.1 absolute maximum ratings ............................................................................. 38 20.2 parameter interpretation ............................................................................. 38 20.3 dc characteristics ........................................................................................... 38 20.3.1 a/d converter characteristics ...................................................................................... 40 20.4 ac characteristics ............................................................................................ 41 20.4.1 definition of internal timing ......................................................................................... 4 2 20.4.2 clock generation modes ............................................................................................. 42
st10c167 3/66 20.4.3 prescaler operation .................................................................................................... 43 20.4.4 direct drive ........................................................................................................... ...... 43 20.4.5 oscillator watchdog (owd) ........................................................................................ 43 20.4.6 phase locked loop ...................................................................................................... 43 20.4.7 memory cycle variables .............................................................................................. 44 20.4.8 external clock drive xtal1 ........................................................................................ 45 20.4.9 multiplexed bus ........................................................................................................ ... 46 20.4.10 demultiplexed bus ..................................................................................................... .52 20.4.11 clkout and ready ................................................................................................. 58 20.4.12 external bus arbitration .............................................................................................. .60 20.4.13 high-speed synchronous serial interface (ssc) timing .............................................. 61 21 package mechanical data ........................................................................... 64 22 ordering information....................................................................................... 65
st10c167 4/66 1 - introduction the st10c167 is a derivative of the stmicroelectronics st10 family of 16-bit single-chip cmos microcontrollers. it combines high cpu performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced i/o capabilities. it also provides on-chip high-speed ram and clock generation via pll. figure 1 : logic symbol xtal1 rstin xtal2 rstout nmi ea ready ale rd wr /wrl port 5 16-bit port 6 8-bit port 4 8-bit port 3 15-bit port 2 16-bit port 1 16-bit port 0 16-bit v dd v ss port 7 8-bit port 8 8-bit v aref v agnd st10c167 rpd
st10c167 5/66 2 - pin data figure 2 : pin configuration (top view) p6.0/cs0 p6.1/cs1 p6.2/cs2 p6.3/cs3 p6.4/cs4 p6.5/hold p6.6/hlda p6.7/breq p8.0/cc16io p8.1/cc17io p8.2/cc18io p8.3/cc19io p8.4/cc20io p8.6/cc22io p8.7/cc23io v dd v ss p7.0/pout0 p7.1/pout1 p7.2/pout2 p7.3/pout3 p8.5/cc21io rpd p7.4/cc28i0 p7.5/cc29i0 p7.6/cc30i0 p7.7/cc31i0 p5.0/an0 p5.1/an1 p5.2/an2 p5.3/an3 p5.4/an4 p5.5/an5 p5.6/an6 p5.7/an7 p5.8/an8 p5.9/an9 p0h.0/ad8 p0l.7/ad7 p0l.6/ad6 p0l.5/ad5 p0l.4/ad4 p0l.3/ad3 p0l.2ad2 p0l.a/ad1 p0l.0/ad0 ea ale ready wr/wrl rd v ss v dd p4.7/a23 p4.6 a22/can_txd p4.5 a21/can_rxd p4.4/a20 p4.3/a19 p4.2/a18 p4.1/a17 p4.0/a16 v ss v dd p3.15/clkout p3.13/sclk p3.12/bhe /wrh p3.11/rxd0 p3.10/txd0 p3.9/mtsr p3.8/mrst p3.7/t2in p3.6/t3in v aref v agnd p5.10/an10/t6eud p5.11/an11/t5eud p5.12/an12/t6in p5.13/an13/t5in p5.14/an14/t4eud p5.15/an15/t2eud v ss v dd p2.0/cc0io p2.1/cc1io p2.2/cc2io p2.3/cc3io p2.4/cc4io p2.5/cc5io p2.6/cc6io p2.7/cc7io v ss v dd p2.8/cc8io/ex0in p2.9/cc9io/ex1in p2.10/cc10ioex2in p2.11/cc11ioex3in p2.12/cc12io/ex4in p2.13/cc13io/ex5in p2.14/cc14io/ex6in p2.15/cc15io/ex7in/t7in p3.0/t0in p3.1/t6out p3.2/capin p3.3/t3out p3.4/t3eud p3.5/t4in v ss v dd v ss nmi v dd rstout rstin v ss xtal1 xtal2 v dd p1h.7/a15/cc27io p1h.6/a14/cc26io p1h.5/a13/cc25io p1h.4/a12/cc24io p1h.3/a11 p1h.2/a10 p1h.1/a9 p1h.0/a8 v ss v dd p1l.7/a7 p1l.6/a6 p1l.5/a5 p1l.4/a4 p1l.3/a3 p1l.2/a2 p1l.1/a1 p1l.0/a0 p0h.7/ad15 p0h.6/ad14 p0h.5/ad13 p0h.4/ad12 p0h.3/ad11 p0h.2/ad10 p0h.1/ad9 v ss v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 st10c167
st10c167 6/66 table 1 : pin list symbol pin type function p6.0 - p6.7 1 - 8 i/o 8-bit bidirectional i/o port, bit-wise programmable for input or output via direction bits. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 6 outputs can be configured as push/pull or open drain drivers. the following port 6 pins have alternate functions: 1 ... 5 6 7 8 o ... o i o o p6.0 cs0 chip select 0 output ... ... ... p6.4 cs4 chip select 4 output p6.5 hold external master hold request input p6.6 hlda hold acknowledge output p6.7 breq bus request output p8.0 - p8.7 9 - 16 i/o 8-bit bidirectional i/o port, bit-wise programmable for input or output via direction bits. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 8 outputs can be configured as push/pull or open drain drivers. the input threshold of port 8 is selectable (ttl or special). the following port 8 pins have alternate functions: 9 ... 16 i/o ... i/o p8.0 cc16io capcom2: cc16 capture input/compare output ... ... ... p8.7 cc23io capcom2: cc23 capture input/compare output p7.0 - p7.7 19 - 26 i/o 8-bit bidirectional i/o port, bit-wise programmable for input or output via direction bits. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 7 outputs can be configured as push/pull or open drain drivers. the input threshold of port 7 is selectable (ttl or special). the following port 7 pins have alternate functions: 19 ... 22 23 ... 26 o ... o i/o ... i/o p7.0 pout0 pwm channel 0 output ... ... ... p7.3 pout3 pwm channel 3 output p7.4 cc28io capcom2: cc28 capture input/compare output ... ... ... p7.7 cc31io capcom2: cc31 capture input/compare output p5.0 - p5.9 p5.10 - p5.15 27 - 36 39 - 44 i i port 5 is a 16-bit input-only port with schmitt-trigger characteristics. the pins of port 5 also serve as the (up to 16) analog input channels for the a/ d converter, where p5.x equals anx (analog input channel x), or they serve as timer inputs: 39 40 41 42 43 44 i i i i i i p5.10 t6eud gpt2 timer t6 external up/down control input p5.11 t5eud gpt2 timer t5 external up/down control input p5.12 t6in gpt2 timer t6 count input p5.13 t5in gpt2 timer t5 count input p5.14 t4eud gpt1 timer t4 external up/down control input p5.15 t2eud gpt1 timer t2 external up/down control input
st10c167 7/66 p2.0 - p2.7 p2.8 - p2.15 47 - 54 57 - 64 i/o 16-bit bidirectional i/o port, bit-wise programmable for input or output via direction bits. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 2 outputs can be configured as push/pull or open drain drivers. the input threshold of port 2 is selectable (ttl or special). the following port 2 pins have alternate functions: 47 ... 54 57 ... 64 i/o ... i/o i/o i ... i/o i i p2.0 cc0io capcom: cc0 capture input/compare output ... ... ... p2.7 cc7io capcom: cc7 capture input/compare output p2.8 cc8io capcom: cc8 capture input/compare output ex0in fast external interrupt 0 input ... ... ... p2.15 cc15io capcom: cc15 capture input/compare output ex7in fast external interrupt 7 input t7in capcom2 timer t7 count input p3.0 - p3.5 p3.6 - p3.13 p3.15 65 - 70 73 - 80 81 i/o i/o i/o 15-bit (p3.14 is missing) bidirectional i/o port, bit-wise programmable for input or output via direction bits. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 3 outputs can be configured as push/pull or open drain drivers. the input threshold of port 3 is selectable (ttl or special). the following port 3 pins have alternate functions: 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 i o i o i i i i i/o i/o i/o o o i/o o p3.0 t0in capcom timer t0 count input p3.1 t6out gpt2 timer t6 toggle latch output p3.2 capin gpt2 register caprel capture input p3.3 t3out gpt1 timer t3 toggle latch output p3.4 t3eud gpt1 timer t3 external up/down control input p3.5 t4in gpt1 timer t4 input for count/gate/reload/capture p3.6 t3in gpt1 timer t3 count/gate input p3.7 t2in gpt1 timer t2 input for count/gate/reload/capture p3.8 mrst ssc master-receive/slave-transmit i/o p3.9 mtsr ssc master-transmit/slave-receive o/i p3.10 txd0 asc0 clock/data output (asynchronous/synchronous) p3.11 rxd0 asc0 data input (asyn.) or i/o (synchronous) p3.12 bhe external memory high byte enable signal, wrh external memory high byte write strobe p3.13 sclk ssc master clock output/slave clock input p3.15 clkout system clock output (=cpu clock) p4.0 - p4.7 85 - 92 i/o 8-bit bidirectional i/o port, bit-wise programmable for input or output via direction bits. programming an i/o pin as input forces the corresponding output driver to high impedance state. for external bus configuration, port 4 can be used to output the segment address lines: 85 - 89 90 91 92 o o i o o o p4.0 - p4.4 a16 - a20 least significant segment address line p4.5 a21 segment address line can_rxd can receive data input p4.6 a22 segment address line, can_txd can transmit data output p4.7 a23 most significant segment address line rd 95 o external memory read strobe. rd is activated for every external instruc- tion or data read access. table 1 : pin list (continued) symbol pin type function
st10c167 8/66 wr /wrl 96 o external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl -mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in register syscon for mode selection. ready/ready 97 i ready input. the active level is programmable. when the ready function is enabled, the selected inactive level at this pin during an external mem- ory access will force the insertion of memory cycle time waitstates until the pin returns to the selected active level. ale 98 o address latch enable output. can be used for latching the address into external memory or an address latch in the multiplexed bus modes. ea 99 i external access enable pin. a low level at this pin during and after reset forces the st10c167 to begin instruction execution out of external mem- ory. a high level forces execution out of the internal flash memory. p0l.0 - p0l.7 p0h.0 p0h.1 - p0h.7 100 - 107 108 111 - 117 i/o port 0 consists of the two 8-bit bidirectional i/o ports p0l and p0h. it is bit-wise programmable for input or output via direction bits. for a pin con- figured as input, the output driver is put into high-impedance state. in case of an external bus configuration, port 0 serves as the address (a) and address/data (ad) bus in multiplexed bus modes and as the data (d) bus in demultiplexed bus modes. demultiplexed bus modes: data path width : 8-bit 16-bit p0l.0 C p0l.7 : d0 C d7 d0 - d7 p0h.0 C p0h.7 : i/o d8 - d15 multiplexed bus modes: data path width : 8-bit 16-bit p0l.0 C p0l.7 : ad0 C ad7 ad0 - ad7 p0h.0 C p0h.7 : a8 - a15 ad8 - ad15 p1l.0 - p1l.7 p1h.0 - p1h.7 118 - 125 128 - 135 i/o port 1 consists of the two 8-bit bidirectional i/o ports p1l and p1h. it is bit-wise programmable for input or output via direction bits. for a pin con- figured as input, the output driver is put into high-impedance state. port 1 is used as the 16-bit address bus (a) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. the following port1 pins also serve for alternate functions: 132 133 134 135 i i i i p1h.4 cc24io capcom2: cc24 capture input p1h.5 cc25io capcom2: cc25 capture input p1h.6 cc26io capcom2: cc26 capture input p1h.7 cc27io capcom2: cc27 capture input xtal1 138 i input to the oscillator amplifier and input to the internal clock generator xtal2 137 o output of the oscillator amplifier circuit. to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. minimum and maximum high/low and rise/fall times specified in the ac characteristics must be observed. rstin 140 i reset input with schmitt-trigger characteristics. a low level at this pin for a specified duration while the oscillator is running resets the st10c167. an internal pullup resistor permits power-on reset using only a capacitor connected to v ss . in bidirectional reset mode (enabled by setting bit bdrsten in syscon register), the rstin line is pulled low for the duration of the internal reset sequence. table 1 : pin list (continued) symbol pin type function
st10c167 9/66 rstout 141 o internal reset indication output. this pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog-timer reset. rstout remains low until the einit (end of initialization) instruc- tion is executed. nmi 142 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. if bit pwdcfg = 0 in syscon register, when the pwrdn (power down) instruction is exe- cuted, the nmi pin must be low in order to force the st10c167 to go into power down mode. if nmi is high and pwdcfg =0, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. v aref 37 - reference voltage for the a/d converter. v agnd 38 - reference ground for the a/d converter. rpd 84 - this pin is used as the timing pin for the return from powerdown circuit and power-up asynchronous reset. v dd 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 - digital supply voltage: = + 5v during normal operation and idle mode. > + 2.5v during power down mode v ss 18, 45, 55, 71, 83, 94, 110, 127, 139, 143 - digital ground. table 1 : pin list (continued) symbol pin type function
st10c167 10/66 3 - functional description the architecture of the st10c167 combines advantages of both risc and cisc processors and an advanced peripheral subsystem. the block diagram gives an overview of the different on-chip components and the high bandwidth inter- nal bus structure of the st10c167. figure 3 : block diagram port 0 por t 1 por t 4 port 6 port 5 port 3 port 2 gpt1 gpt2 asc usart brg cpu-core internal ram watchdog interrupt controller 32 16 pec 16 16 can port 7 port 8 external bus 10-bit adc brg ssc pwm capcom2 capcom1 osc. 2k byte 16 controller 16 16 32k byte rom for st10c167 xram xtal1 xtal2 can_rxd can_txd 8 16 16 16 8 15 8 8
st10c167 11/66 4 - memory organization the memory space of the st10c167 is configured in a von-neumann architecture. code memory, data memory, registers and i/o ports are organized within the same linear address space of 16m byte. the entire memory space can be accessed byte- wise or wordwise. particular portions of the on-chip memory have additionally been made directly bit addressable. rom : 32k byte of on-chip rom. ram : 2k byte of on-chip internal ram (dual-port) is provided as a storage for data, sys- tem stack, general purpose register banks and code. the register bank can consist of up to 16 wordwide (r0 to r15) and/or bytewide (rl0, rh0, , rl7, rh7) general purpose registers. xram : 2k byte of on-chip extension ram (sin- gle port xram) is provided as a storage for data, user stack and code. the xram is connected to the internal xbus and is accessed like an external memory in 16-bit demultiplexed bus-mode without waitstate or read/write delay (80ns access at 25mhz cpu clock). byte and word access is allowed. the xram address range is 00e000h - 00e7ffh if the xram is enabled ( xpen bit 2 of syscon register). as the xram appears like external memory, it cannot be used for the st10c167s system stack or register banks. the xram is not provided for single bit storage and therefore is not bit addressable. if bit xramen is cleared, then any access in the address range 00e000h - 00e7ffh will be directed to external memory interface, using the busconx register corresponding to address matching addrselx register. sfr/esfr : 1024 byte (2 * 512 byte) of address space is reserved for the special function register areas. sfrs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. can : address range 00ef00h - 00efffh is reserved for the can module access. the can is enabled by setting xpen bit 2 of the syscon register. accesses to the can module use demul- tiplexed addresses and a 16-bit data bus (byte accesses are possible). two wait states give an access time of 160ns at 25mhz cpu clock. no tristate waitstate is used. note if the can module is used, port 4 can not be programmed to output all 8 segment address lines. thus, only 4 segment address lines can be used, reducing the external memory space to 5m byte (1m byte per cs line). in order to meet the needs of designs where more memory is required than is provided on chip, up to 16m byte of external ram and/or rom can be connected to the microcontroller.
st10c167 12/66 5 - central processing unit (cpu) the cpu includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (alu) and dedi- cated sfrs. additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. most of the st10c167s instructions can be exe- cuted in one instruction cycle which requires 80ns at 25mhz cpu clock. for example, shift and rotate instructions are processed in one instruc- tion cycle independent of the number of bits to be shifted. multiple-cycle instructions have been opti- mized: branches are carried out in 2 cycles, 16 x 16 bit multiplication in 5 cycles and a 32/16 bit division in 10 cycles.the jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. the cpu uses an actual register context consisting of up to 16 word wide gprs physically allocated within the on-chip ram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 1024 byte is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. figure 4 : cpu block diagram 32 internal ram 2k byte general purpose registers r0 r15 mdh mld barrel-shift mul./div.-hw bit-mask gen. alu 16-bit cp sp stkov stkun exec. unit instr. ptr instr. reg 4-stage pipeline psw syscon buscon 0 buscon 1 buscon 2 buscon 3 buscon 4 addrsel 1 addrsel 2 addrsel 3 addrsel 4 data pg. ptrs code seg. ptr. cpu 32k byte on chip rom 16 16 bank n bank i bank 0
st10c167 13/66 6 - external bus controller all of the external memory accesses are per- formed by the on-chip external bus controller. the ebc can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes: C 16-/18-/20-/24-bit addresses and 16-bit data, demultiplexed. C 16-/18-/20-/24-bit addresses and 16-bit data, multiplexed. C 16-/18-/20-/24-bit addresses and 8-bit data, multiplexed. C 16-/18-/20-/24-bit addresses and 8-bit data, de- multiplexed. in demultiplexed bus modes addresses are output on port1 and data is input/output on port0 or p0l, respectively. in the multiplexed bus modes both addresses and data use port0 for input/output. timing characteristics of the external bus inter- face (memory cycle time, memory tri-state time, length of ale and read/write delay) are program- mable giving the choice of a wide range of memo- ries and external peripherals. up to 4 independent address windows may be defined (using register pairs addrselx / busconx) to access different resources and bus characteristics. these address windows are arranged hierarchically where buscon4 overrides buscon3 and buscon2 overrides buscon1. all accesses to locations not covered by these 4 address windows are con- trolled by buscon0. up to 5 external cs signals (4 windows plus default) can be generated in order to save external glue logic. access to very slow memories is supported by a ready function. a hold /hlda protocol is available for bus arbi- tration which shares external resources with other bus masters. the bus arbitration is enabled by setting bit hlden in register syscon. after set- ting hlden once, pins p6.7...p6.5 (breq , hlda , hold ) are automatically controlled by the ebc. in master mode (default after reset) the hlda pin is an output. by setting bit dp6.7 to1 the slave mode is selected where pin hlda is switched to input. this directly connects the slave controller to another master controller without glue logic. for applications which require less external mem- ory space, the address space can be restricted to 1m byte, 256k byte or to 64k byte. port 4 outputs all 8 address lines if an address space of 16m byte is used, otherwise four, two or no address lines. chip select timing can be made programmable. by default (after reset), the csx lines change half a cpu clock cycle after the rising edge of ale. with the cscfg bit set in the syscon register the csx lines change with the rising edge of ale. the active level of the ready pin can be set by bit rdypol in the busconx registers. when the ready function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit rdypol in the associated buscon register.
st10c167 14/66 7 - interrupt system the interrupt response time for internal program execution is from 200ns to 480ns. the st10c167 architecture supports several mechanisms for fast and flexible response to ser- vice requests that can be generated from various sources internal or external to the microcontroller. any of these interrupt requests can be serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is stolen from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an addi- tional increment of either the pec source or the destination pointer. an individual pec transfer counter is implicitly decremented for each pec service except when performing in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the correspond- ing source related vector location. pec services are very well suited, for example, for supporting the transmission or reception of blocks of data. the st10c167 has 8 pec channels each of which offers such fast interrupt-driven data trans- fer capabilities. a interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield is dedicated to each existing interrupt source. thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. once starting to be processed by the cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. fast external interrupt inputs are provided to ser- vice external interrupts with high precision requirements. these fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). software interrupts are supported by means of the trap instruction in combination with an individ- ual trap (interrupt) number. table 2 shows all the available st10c167 inter- rupt sources and the corresponding hard- ware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers : table 2 : interrupt sources source of interrupt or pec service request request flag enable flag interrupt vector vector location tr a p number capcom register 0 cc0ir cc0ie cc0int 000040h 10h capcom register 1 cc1ir cc1ie cc1int 000044h 11h capcom register 2 cc2ir cc2ie cc2int 000048h 12h capcom register 3 cc3ir cc3ie cc3int 00004ch 13h capcom register 4 cc4ir cc4ie cc4int 000050h 14h capcom register 5 cc5ir cc5ie cc5int 000054h 15h capcom register 6 cc6ir cc6ie cc6int 000058h 16h capcom register 7 cc7ir cc7ie cc7int 00005ch 17h capcom register 8 cc8ir cc8ie cc8int 000060h 18h capcom register 9 cc9ir cc9ie cc9int 000064h 19h capcom register 10 cc10ir cc10ie cc10int 000068h 1ah capcom register 11 cc11ir cc11ie cc11int 00006ch 1bh capcom register 12 cc12ir cc12ie cc12int 000070h 1ch capcom register 13 cc13ir cc13ie cc13int 000074h 1dh capcom register 14 cc14ir cc14ie cc14int 000078h 1eh capcom register 15 cc15ir cc15ie cc15int 00007ch 1fh capcom register 16 cc16ir cc16ie cc16int 0000c0h 30h capcom register 17 cc17ir cc17ie cc17int 0000c4h 31h
st10c167 15/66 capcom register 18 cc18ir cc18ie cc18int 0000c8h 32h capcom register 19 cc19ir cc19ie cc19int 0000cch 33h capcom register 20 cc20ir cc20ie cc20int 0000d0h 34h capcom register 21 cc21ir cc21ie cc21int 0000d4h 35h capcom register 22 cc22ir cc22ie cc22int 0000d8h 36h capcom register 23 cc23ir cc23ie cc23int 0000dch 37h capcom register 24 cc24ir cc24ie cc24int 0000e0h 38h capcom register 25 cc25ir cc25ie cc25int 0000e4h 39h capcom register 26 cc26ir cc26ie cc26int 0000e8h 3ah capcom register 27 cc27ir cc27ie cc27int 0000ech 3bh capcom register 28 cc28ir cc28ie cc28int 0000e0h 3ch capcom register 29 cc29ir cc29ie cc29int 000110h 44h capcom register 30 cc30ir cc30ie cc30int 000114h 45h capcom register 31 cc31ir cc31ie cc31int 000118h 46h capcom timer 0 t0ir t0ie t0int 000080h 20h capcom timer 1 t1ir t1ie t1int 000084h 21h capcom timer 7 t7ir t7ie t7int 0000f4h 3dh capcom timer 8 t8ir t8ie t8int 0000f8h 3eh gpt1 timer 2 t2ir t2ie t2int 000088h 22h gpt1 timer 3 t3ir t3ie t3int 00008ch 23h gpt1 timer 4 t4ir t4ie t4int 000090h 24h gpt2 timer 5 t5ir t5ie t5int 000094h 25h gpt2 timer 6 t6ir t6ie t6int 000098h 26h gpt2 caprel register crir crie crint 00009ch 27h a/d conversion complete adcir adcie adcint 0000a0h 28h a/d overrun error adeir adeie adeint 0000a4h 29h asc0 transmit s0tir s0tie s0tint 0000a8h 2ah asc0 transmit buffer s0tbir s0tbie s0tbint 00011ch 47h asc0 receive s0rir s0rie s0rint 0000ach 2bh asc0 error s0eir s0eie s0eint 0000b0h 2ch ssc transmit sctir sctie sctint 0000b4h 2dh ssc receive scrir scrie scrint 0000b8h 2eh ssc error sceir sceie sceint 0000bch 2fh pwm channel 0...3 pwmir pwmie pwmint 0000fch 3fh can interface xp0ir xp0ie xp0int 000100h 40h x-peripheral node xp1ir xp1ie xp1int 000104h 41h x-peripheral node xp2ir xp2ie xp2int 000108h 42h pll unlock xp3ir xp3ie xp3int 00010ch 43h table 2 : interrupt sources (continued) source of interrupt or pec service request request flag enable flag interrupt vector vector location tr a p number
st10c167 16/66 hardware traps are exceptions or error conditions that arise during run-time. they cause immediate non-maskable system reaction similar to a stan- dard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag regis- ter (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. in turn, hardware trap services can normally not be inter- rupted by standard or pec interrupts. table 3 shows all of the possible exceptions or error conditions that can arise during run-time: table 3 : exceptions or error conditions that can arise during run time exception condition trap flag tr a p vector vector location trap number tr a p priority reset functions: hardware reset software reset watchdog timer overflow reset reset reset 000000h 000000h 000000h 00h 00h 00h iii iii iii class a hardware tra ps: non-maskable interrupt stack overflow stack underflow nmi stkof stkuf nmitrap stotrap stutrap 000008h 000010h 000018h 02h 04h 06h ii ii ii class b hardware tra ps: undefined opcode protected instruction fault illegal word operand access illegal instruction access illegal external bus access undopc prtflt illopa illina illbus btrap btrap btrap btrap btrap 000028h 000028h 000028h 000028h 000028h 0ah 0ah 0ah 0ah 0ah i i i i i reserved [2ch C3ch] [0bh C 0fh] software traps trap instruction any [000000hC 0001fch] in steps of 4h any [00h C 7fh] current cpu priority
st10c167 17/66 8 - capture/compare (capcom) unit the st10c167 has two 16 channel capcom units. they support generation and control of timing sequences on up to 32 channels with a maximum resolution of 320ns at 25mhz cpu clock. the capcom units are typically used to handle high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw), digital to analog (d/a) conversion, software timing, or time recording relative to external events. four 16-bit timers (t0/t1, t7/t8) with reload registers provide two independent time bases for the capture/compare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/ underflow of timer t6 in module gpt2. this provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. in addition, external count inputs for capcom timers t0 and t7 allow event scheduling for the capture/compare registers relative to external events. each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either capcom timer t0 or t1 (t7 or t8, respectively), and programmed for capture or compare functions. each register has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin (except for cc24...cc27) to indicate the occurrence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture/ compare register, specific actions will be taken based on the selected compare mode (see ta b l e 4 ) . the input frequencies f tx for tx are determined as a function of the cpu clocks. the formulas are detailed in the user manual. the timer input fre- quencies, resolution and periods which result from the selected pre-scaler option in txi when using a 25mhz cpu clock are listed in the table below. the numbers for the timer periods are based on a reload value of 0000 h . note that some numbers may be rounded to 3 significant figures (see table 5). table 4 : compare modes compare modes function mode 0 interrupt-only compare mode ; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match ; several compare events per timer period are possible mode 2 interrupt-only compare mode ; only one compare interrupt per timer period is generated mode 3 pin set 1 on match; pin reset 0 on compare time overflow ; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match ; several compare events per timer period are possible. table 5 : capcom timer input frequencies, resolution and periods f cpu = 25mhz timer input selection txi 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b pre-scaler for f cpu 8 16 32 64 128 256 512 1024 input frequency 3.125mhz 1.56mhz 781khz 391khz 195khz 97.7khz 48.8khz 24.4khz resolution 320ns 640ns 1.28 m s 2.56 m s 5.12 m s 10.24 m s 20.48 m s 40.96 m s period 21.0ms 41.9ms 83.9ms 167ms 336ms 671ms 1.34s 2.68s
st10c167 18/66 9 - general purpose timer unit the gpt unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gpt unit contains five 16-bit timers organized into two separate modules gpt1 and gpt2. each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. 9.1 - gpt1 each of the three timers t2, t3, t4 of the gpt1 module can be configured individually for one of four basic modes of operation: timer , gated timer , counter mode and incremental interface mode . in timer mode, the input clock for a timer is derived from the cpu clock, divided by a pro- grammable prescaler. in counter mode, the timer is clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the gate level on an external input pin. for these purposes, each timer has one asso- ciated port pin (txin) which is the gate or the clock input. the table below lists the timer input frequencies, resolution and periods for each pre-scaler option at 25mhz cpu clock. this also applies to the gated timer mode of t3 and to the auxiliary timers t2 and t4 in timer and gated timer mode (see table 6). the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud). in incremental interface mode, the gpt1 timers (t2, t3, t4) can be directly connected to the incremental position sensor signals a and b by their respective inputs txin and txeud. direction and count signals are internally derived from these two input signals so that the contents of the respective timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has output toggle latches (txotl) which changes state on each timer over-flow/underflow. the state of this latch may be output on port pins (txout) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers t2 and t4 for high resolution mea- surement of long time periods. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is reloaded with the contents of t2 or t4 triggered either by an external signal or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated without software intervention. table 6 : gpt1 timer input frequencies, resolution and periods f cpu = 25mhz timer input selection t2i / t3i / t4i 000 b 001 b 010 b 011 b 100 b 101 b 110 b 111 b pre-scaler factor 8 16 32 64 128 256 512 1024 input frequency 3.125mhz 1.563mhz 781.3khz 390.6khz 195.3khz 97.66khz 48.83khz 24.41khz resolution 320ns 640ns 1.28 m s 2.56 m s5.12 m s 10.24 m s 20.48 m s 40.96 m s period 21.0ms 41.9ms 83.9ms 167ms 336ms 671ms 1.34s 2.68s
st10c167 19/66 9.2 - gpt2 the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock via a programmable prescaler or with external signals. the count direction (up/down) for each timer is programma- ble by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is sup- ported via the output toggle latch (t6otl) of timer t6 which changes its state on each timer over- flow/underflow. the state of this latch may be used to clock timer t5, or it may be output on a port pin (t6out). the overflows/underflows of timer t6 can additionally be used to clock the capcom timers t0 or t1, and to cause a reload from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture proce- dure. this allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. the capture trigger (timer t5 to caprel) may also be generated upon transitions of gpt1 timer t3 inputs t3in and/or t3eud. this is advanta- geous when t3 operates in incremental interface mode. table 7 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25mhz cpu clock. this also applies to the gated timer mode of t6 and to the auxiliary timer t5 in timer and gated timer mode. figure 5 : block diagram of gpt1 2 n n=3...10 2 n n=3...10 2 n n=3...10 t2eud t2in cpu clock cpu clock cpu clock t3eud t4in t3in t4eud t2 mode control t3 mode control t4 mode control gpt1 timer t2 gpt1 timer t3 gpt1 timer t4 t3otl reload capture u/d u/d reload capture interrupt request interrupt request interrupt request t3out u/d
st10c167 20/66 table 7 : gpt2 timer input frequencies, resolution and periods f cpu = 25mhz timer input selection t5i / t6i 000b 001b 010b 011b 100b 101b 110b 111b pre-scaler factor 4 8 16 32 64 128 256 512 input frequency 6.25mhz 3.125mhz 1.563mhz 781.3khz 390.6khz 195.3khz 97.66khz 48.83khz resolution 160ns 320ns 640ns 1.28 m s 2.56 m s 5.12 m s 10.24 m s20.48 m s period 10.49ms 21.0ms 41.9ms 83.9ms 167ms 336ms 671ms 1.34s figure 6 : block diagram of gpt2 2 n n=2...9 2 n n=2...9 t5eud t5in cpu clock cpu clock t6in t6eud t5 mode control t6 mode control gpt2 timer t5 gpt2 timer t6 u/d interrupt request u/d gpt2 caprel t60tl toggle ff t6out capin reload interrupt request to capcom timers capture clear interrupt request
st10c167 21/66 10 - pwm module the pulse width modulation module can generate up to four pwm output signals using edge-aligned or centre-aligned pwm. in addition, the pwm module can generate pwm burst signals and sin- gle shot outputs. table 8 shows the pwm fre- quencies for different resolutions. the level of the output signals is selectable and the pwm module can generate interrupt requests. table 8 : pwm unit frequencies and resolution at 25mhz clock mode 0 resolution 8-bit 10-bit 12-bit 14-bit 16-bit cpu clock/1 40ns 97.66khz 24.41khz 6.104khz 1.526khz 0.381khz cpu clock/64 2.56ns 1.526khz 381.5hz 95.37hz 23.84hz 5.96hz mode 1 resolution 8-bit 10-bit 12-bit 14-bit 16-bit cpu clock/1 40ns 48.82khz 12.20khz 3.05khz 762.9hz 190.7hz cpu clock/64 2.56ns 762.9hz 190.7 hz 47.68hz 11.92hz 2.98hz figure 7 : block diagram of pwm module ppx period register comparator ptx 16-bit up/down counter shadow register pwx pulse width register input run control clock 1 clock 2 comparator * * * up/down/ clear control match output control match write control * user read-& writeable enable poutx
st10c167 22/66 11 - parallel ports the st10c167 provides up to 111 i/o lines orga- nized into eight input/output ports and one input port. all port lines are bit-addressable, and all input/out- put lines are individually (bit-wise) programmable as input or output via direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when config- ured as inputs. the output drivers of five i/o ports can be config- ured (pin by pin) for push/pull operation or open-drain operation via control registers. during the internal reset, all port pins are configured as inputs. the input threshold of port 2, port 3, port 7 and port 8 is selectable (ttl-or cmos-like), where the special cmos-like input threshold reduces noise sensitivity due to the input hysteresis. the input thresholds are selected with bit of picon register dedicated to blocks of 8 input pins (2-bit for port2, 2-bit for port3, 1-bit for port7, 1-bit for port8). all pins of i/o ports also support an alternate pro- grammable function: C port0 and port1 may be used as address and data lines when accessing external memory. C port 2, port 7 and port 8 are associated with the capture inputs or with the compare outputs of the capcom units and/or with the outputs of the pwm module. C port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal bhe and the system clock output (clkout). C port 4 outputs the additional segment address bits a16 to a23 in systems where segmentation is enabled to access more than 64k byte of memory. C port 5 is used as analog input channels of the a/d converter or as timer control signals. C port 6 provides optional bus arbitration signals (breq , hlda , hold ) and chip select signals. all port lines that are not used for alternate func- tions may be used as general purpose i/o lines.
st10c167 23/66 12 - a/d converter a10-bit a/d converter with 16 multiplexed input channels and a sample and hold circuit is inte- grated on-chip. the sample time (for loading the capacitors) and the conversion time is program- mable and can be adjusted to the external circuitry. overrun error detection/protection is controlled by the addat register. either an interrupt request is generated when the result of a previous conver- sion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. for applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. the ad converter of the st10f168 supports different conversion modes : C single channel single conversion : the analog level of the selected channel is sampled once and converted. the result of the conversion is stored in the addat register. C single channel continuous conversion : the analog level of the selected channel is repeatedly sampled and converted. the result of the conver- sion is stored in the addat register. C auto scan single conversion : the analog level of the selected channels are sampled once and converted. after each conversion the result is stored in the addat register. the data can be transfered to the ram by interrupt software management or using the powerfull peripheral event controller data transfert. C auto scan continuous conversion : the ana- log level of the selected channels are repeatedly sampled and converted. the result of the con- version is stored in the addat register. the data can be transfered to the ram by interrupt software management or using the powerfull peripheral event controller data transfert. C wait for addat read mode : when using con- tinuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the adwr bit of adcon control register must be activated. then, until the addat regis- ter is read, the new result is stored in a tempo- rary buffer and the conversion is on hold. C channel injection mode : when using continuous modes, a selected channel can be converted in between without changing the current operating mode. the 10 bit data of the conversion are stored in adres field of addat2. the current continuous mode remains active after the single conversion is completed. the table : 9 adc sample clock and conversion time shows the adc unit conversion clock, sample clock. a complete conversion will take 14t cc + 2 t sc + 4 tcl. this time includes the conversion it-self, the sampling time and the time required to trans- fer the digital value to the result register. for example, at 25mhz of cpu clock, minimum com- plete conversion time is 7.76 m s. the a/d converter provides automatic offset and linearity self calibration. the calibration operation is performed in two ways: C a full calibration sequence is performed after a reset and lasts 1.6ms minimum (at 25mhz cpu clock). during this time, the adbsy flag is set to indicate the operation. normal conversion can be performed during this time. the duration of the calibration sequence is then extended by the time consumed by the conversions. note : after a power-on reset, the total unadjusted error (tue) of the adc might be worse than 2lsb (max. 4lsb). during the full calibration sequence, the tue is constantly improved until at the end of the cycle, tue is within the specified limits of 2lsb. C one calibration cycle is performed after each conversion : each calibration cycle takes 4 adc clock cycles. these operation cycles ensure constant updating of the adc accuracy, com- pensating changing operating conditions. note 1. see section 20.4.4 - direct drive on page 43. 2. t cc = tcl x 24. table 9 : adc sample clock and conversion time adctc conversion clock t cc adstc sample clock t sc tcl 1 = 1/2 x f xtal at f cpu = 25mhz t sc = at f cpu = 25mhz 00 tcl x 24 0.48 m s00 t cc 0.48 m s 2 01 reserved, do not use - 01 t cc x 2 0.96 m s 2 10 tcl x 96 1.92 m s10t cc x 4 1.92 m s 2 11 tcl x 48 0.96 m s11t cc x 8 3.84 m s 2
st10c167 24/66 13 - serial channels serial communication with other microcontrollers, processors, terminals or external peripheral com- ponents is provided by two serial interfaces: the asynchronous/synchronous serial channel (asc0) and the high-speed synchronous serial channel (ssc). two dedicated baud rate generators set up all standard baud rates without the requirement of oscillator tuning. for transmission, reception and erroneous recep- tion, 3 separate interrupt vectors are provided for each serial channel. asco asco supports full-duplex asynchronous communication up to 781.25k baud and half-duplex synchronous communication up to 5m baud at 25mhz system clock. for asynchronous operation, the baud rate generator provides a clock with 16 times the rate of the established baud rate. the table below lists various commonly used baud rates together with the required reload val- ues and the deviation errors compared to the intended baud rate (see table 10). for synchronous operation, the baud rate genera- tor provides a clock with 4 times the rate of the established baud rate. note the deviation errors given in the table above are rounded. using a baud rate crystal will provide correct baud rates withou t deviation errors. table 10 : commonly used baud rates by reload value and deviation errors s0brs = 0, f cpu = 25mhz s0brs = 1, f cpu = 25mhz baud rate (baud) deviation error reload value baud rate (baud) deviation error reload value 781250 0.0% 0000 h 520833 0.0% 0000 h 56000 +7.3% / -0.4% 000c h / 000d h 56000 +3.3% / -7.0% 0008h / 0009h 38400 +1.7% / -3.1% 0013 h / 0014 h 38400 +4.3% / -3.1% 000ch / 000dh 19200 +1.7% / -0.8% 0027 h / 0028 h 19200 +0.5% / -3.1% 001ah / 001bh 9600 +0.5% / -0.8% 0050 h / 0051 h 9600 +0.5% / -1.4% 0035h / 0036h 4800 +0.5% / -0.1% 00a1 h / 00a2 h 4800 +0.5% / -0.5% 006bh / 006ch 2400 +0.2% / -0.1% 0144 h / 0145 h 2400 +0.0% / -0.5% 00d8h / 00d9h 1200 +0.0% / -0.1% 028a h / 028b h 1200 +0.0% / -0.2% 01b1h / 01b2h 600 +0.0% / -0.1% 0515 h / 0516 h 600 +0.0% / -0.1% 0363h / 0364h 95 +0.4% / 0.4% 1fff h / 1fff h 75 +0.0% / 0.0% 1b1fh / 1b20h 63 +0.9% / 0.9% 1fffh / 1fffh
st10c167 25/66 high speed synchronous serial channel (ssc) the high-speed synchronous serial interface ssc provides flexible high-speed serial communication between the st10c167 and other microcontrollers, microprocessors or external peripherals. the ssc supports full-duplex and half-duplex synchronous communication; the serial clock signal can be generated by the ssc itself (master mode) or be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data is double-buffered. a 16-bit baud rate generator provides the ssc with a separate serial clock signal. the serial channel ssc has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent from the timers. sscbr is the dual-function baud rate generator/ reload register. table 11 lists some possible baud rates against the required reload values and the resulting bit times for a 25mhz cpu clock. table 11 : synchronous baud rate and reload values baud rate bit time reload value reserved use a reload value > 0. --- 0000 h 5m baud 200ns 0001 h 3.3m baud 303ns 0002 h 2.5m baud 400ns 0004 h 2m baud 500ns 0005 h 1m baud 1 m s 000b h 100k baud 10 m s 007c h 10k baud 100 m s 04e1 h 1k baud 1ms 30d3 h 190.7 baud 5.2ms ffff h
st10c167 26/66 14 - can module the integrated can module handles the com- pletely autonomous transmission and reception of can frames in accordance with the can specifi- cation v2.0 part b (active) i.e. the on-chip can module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. the can module provides full can functionality on up to 15 message objects. message object 15 can be configured for basic can functionality. both modes provide separate masks for accep- tance filtering, allowing a number of identifiers in full can mode to be accepted and disregarding a number of identifiers in basic can mode. all message objects can be updated independent from other objects and are equipped for the maxi- mum message length of 8 byte. the bit timing is derived from the xclk and is pro- grammable up to a data rate of 1m baud. the can module uses two pins to interface to a bus transceiver. 15 - watchdog timer the watchdog timer is a fail-safe mechanism which prevents the microcontroller from malfunc- tioning for long periods of time. the watchdog timer is always enabled after a reset of the chip and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. therefore, the chip start-up pro- cedure is always monitored. the software must be designed to service the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an inter- nal hardware reset. it pulls the rstout pin low in order to allow external hardware components to be reset. the watchdog timer is 16-bit, clocked with the system clock divided by 2 or 128. the high byte of the watchdog timer register can be set to a pre-specified reload value (stored in wdtrel). each time it is serviced by the application soft- ware, the high byte of the watchdog timer is reloaded. for security, rewrite wdtcon each time before the watchdog timer is serviced table 12 : watchdog time range for 25mhz cpu clock reload value in wdtrel prescaler for f cpu 2 (wdtin = 0) 128 (wdtin = 1) ff h 20.48 m s 1.31ms 00 h 5.24ms 336ms
st10c167 27/66 16 - instruction set summary the table below lists the instructions of the st10c167. the various addressing modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the st10 family programming manual. table 13 : instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide register md by direct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (word/byte operands) 2 / 4 xor(b) bitwise xor, (word/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs move byte operand to word operand with sign extension 2 / 4 movbz move byte operand to word operand. with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indirect/relative if condition is met 4 jmps jump absolute to a code segment 4 j(n)b jump relative if direct bit is (not) set 4 jbc jump relative and clear bit if direct bit is set 4
st10c167 28/66 jnbs jump relative and set bit if direct bit is not set 4 calla, calli, callr call absolute/indirect/relative subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack & call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push, pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segment subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (assumes nmi -pin low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout-pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 table 13 : instruction set summary (continued) mnemonic description bytes
st10c167 29/66 17 - system reset the internal system reset function is invoked either by asserting a hardware reset signal on pin rstin (hardware reset input), by the execution of the srst instruction (software reset) or by an overflow of the watchdog timer. whenever one of these conditions occurs, the microcontroller is reset into its predefined default state. the following type of reset are implemented on the st10c167: asynchronous hardware reset asynchronous reset does not require a stabilized clock signal on xtal1, as it is not internally resyn- chronized. it immediately resets the microcontrol- ler into its default reset state. this asynchronous reset is required upon power-up of the chip and may be used during cat- astrophic situations. the rising edge of the rstin pin is internally resynchronized before exiting the reset condition. therefore, only the entry of this hardware reset is asynchronous. synchronous hardware reset (warm reset) a warm synchronous hardware reset is triggered when the reset input signal rstin is latched low and rpd (pin 84) is high. the i/os are immediately (asynchronously) set in high impedance, rstout is driven low. after negation of rstin is detected, a short transition period elapses, during which pending internal hold states are cancelled and any current internal access cycles are completed, external bus cycles are aborted. then, the internal reset sequence starts for 1024 tcl (512 cpu clock cycles). during this reset sequence, if bit bdrsten was previously set by software (bit 5 in syscon register), rstin pin is driven low and internal reset signal is asserted to reset the microcontroller in its default state. note that after all reset sequences, bit bdrsten is cleared. after the reset sequence has been completed, the rstin input is sampled. if the reset input signal is active at that time the internal reset condition is prolonged until rstin becomes inactive. software reset the reset sequence can be triggered at any time by the protected instruction srst (software reset). this instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system failure. as for a synchronous hardware reset, the reset sequence lasts 1024 tcl (512 cpu clock cycles), and drives the rstin pin low. watchdog timer reset when the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence. unlike hardware and software resets, the watch- dog reset completes a running external bus cycle if this bus cycle either does not use ready , or if ready is sampled active (low) after the pro- grammed waitstates. when ready is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. the internal reset sequence is then started. the watchdog reset cannot occur while the st10c167 is in bootstrap loader mode. bidirectional reset this feature is enabled by bit 3 of the syscon register. the bidirectional reset makes the watch- dog timer reset and software reset externally visi- ble. it is active for the duration of an internal reset sequences caused by a watchdog timer reset and software reset. this means that the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 tcl. the consequence is that during a watchdog timer reset or software reset, the behavior of the st10c167 is equal to an external hardware reset.
st10c167 30/66 18 - power reduction modes two different power reduction modes with differ- ent levels of power reduction can be entered under software control. in idle mode the cpu is stopped, while the peripherals continue their operation. idle mode can be terminated by any reset or interrupt request. in power down mode both the cpu and the peripherals are stopped. power down mode can be configured by software in order to be termi- nated only by a hardware reset or by an external interrupt source on fast external interrupt pins. there are two different operating power down modes: C protected power down mode: selected by set- ting bit pwdcfg in the syscon register to 0. this mode can be used in conjunction with an external power failure signal which pulls the nmi pin low when a power failure is imminent. the microcontroller enters the nmi trap routine and saves the internal state into ram. the trap rou- tine then sets a flag or writes a bit pattern into specific ram locations, and executes the pwrdn instruction. if the nmi pin is still low at this time, power down mode will be entered, if not program execution continues. during power down the voltage at the v cc pins can be lowered to 2.5 v and the contents of the internal ram will still be preserved. C interruptible power down mode: this mode is selected by setting bit pwdcfg in the syscon register. the cpu and peripheral clocks are frozen, and the oscillator and pll are stopped. to exit power down mode with an ex- ternal interrupt, an exxin (x = 7...0) pin has to be asserted for at least 40ns. this signal ena- bles the internal oscillator and pll circuitry, and turns on the weak pull-down. if the interrupt was enabled before entering power down mode, the device executes the interrupt service routine, and then resumes execution after the pwrdn instruction. if the interrupt was disabled, the de- vice executes the instruction following pwrdn instruction, and the interrupt request flag re- mains set until it is cleared by software. all external bus actions are completed before idle or power down mode is entered. however, idle or power down mode is not entered if ready is enabled, but has not been activated during the last bus access.
st10c167 31/66 19 - special function register overview table 14 lists all sfrs which are implemented in the st10c167 in alphabetical order. bit-addressable sfrs are marked with the letter b in column name. sfrs within the extended sfr-space (esfrs) are marked with the letter e in column physical address. an sfr can be specified by its individual mnemonic name. depending on the selected addressing mode, an sfr can be accessed via its physical address (using the data page pointers), or via its short 8-bit address (without using the data page pointers). table 14 : special function registers listed by name name physical address 8-bit address description reset value adcic b ff98h cch a/d converter end of conversion interrupt control register 0000h adcon b ffa0h d0h a/d converter control register 0000h addat fea0h 50h a/d converter result register 0000h addat2 f0a0h e 50h a/d converter 2 result register 0000h addrsel1 fe18h 0ch address select register 1 0000h addrsel2 fe1ah 0dh address select register 2 0000h addrsel3 fe1ch 0eh address select register 3 0000h addrsel4 fe1eh 0fh address select register 4 0000h adeic b ff9ah cdh a/d converter overrun error interrupt control register 0000h buscon0 b ff0ch 86h bus configuration register 0 0xx0h buscon1 b ff14h 8ah bus configuration register 1 0000h buscon2 b ff16h 8bh bus configuration register 2 0000h buscon3 b ff18h 8ch bus configuration register 3 0000h buscon4 b ff1ah 8dh bus configuration register 4 0000h caprel fe4ah 25h gpt2 capture/reload register 0000h cc8ic b ff88h c4h ex0in interrupt control register 0000h cc0 fe80h 40h capcom register 0 0000h cc0ic b ff78h bch capcom register 0 interrupt control register 0000h cc1 fe82h 41h capcom register 1 0000h cc1ic b ff7ah bdh capcom register 1 interrupt control register 0000h cc2 fe84h 42h capcom register 2 0000h cc2ic b ff7ch beh capcom register 2 interrupt control register 0000h cc3 fe86h 43h capcom register 3 0000h cc3ic b ff7eh bfh capcom register 3 interrupt control register 0000h cc4 fe88h 44h capcom register 4 0000h cc4ic b ff80h c0h capcom register 4 interrupt control register 0000h cc5 fe8ah 45h capcom register 5 0000h cc5ic b ff82h c1h capcom register 5 interrupt control register 0000h cc6 fe8ch 46h capcom register 6 0000h cc6ic b ff84h c2h capcom register 6 interrupt control register 0000h cc7 fe8eh 47h capcom register 7 0000h cc7ic b ff86h c3h capcom register 7 interrupt control register 0000h cc8 fe90h 48h capcom register 8 0000h
st10c167 32/66 cc8ic b ff88h c4h capcom register 8 interrupt control register 0000h cc9 fe92h 49h capcom register 9 0000h cc9ic b ff8ah c5h capcom register 9 interrupt control register 0000h cc10 fe94h 4ah capcom register 10 0000h cc10ic b ff8ch c6h capcom register 10 interrupt control register 0000h cc11 fe96h 4bh capcom register 11 0000h cc11ic b ff8eh c7h capcom register 11 interrupt control register 0000h cc12 fe98h 4ch capcom register 12 0000h cc12ic b ff90h c8h capcom register 12 interrupt control register 0000h cc13 fe9ah 4dh capcom register 13 0000h cc13ic b ff92h c9h capcom register 13 interrupt control register 0000h cc14 fe9ch 4eh capcom register 14 0000h cc14ic b ff94h cah capcom register 14 interrupt control register 0000h cc15 fe9eh 4fh capcom register 15 0000h cc15ic b ff96h cbh capcom register 15 interrupt control register 0000h cc16 fe60h 30h capcom register 16 0000h cc16ic b f160h e b0h capcom register 16 interrupt control register 0000h cc17 fe62h 31h capcom register 17 0000h cc17ic b f162h e b1h capcom register 17 interrupt control register 0000h cc18 fe64h 32h capcom register 18 0000h cc18ic b f164h e b2h capcom register 18 interrupt control register 0000h cc19 fe66h 33h capcom register 19 0000h cc19ic b f166h e b3h capcom register 19 interrupt control register 0000h cc20 fe68h 34h capcom register 20 0000h cc20ic b f168h e b4h capcom register 20 interrupt control register 0000h cc21 fe6ah 35h capcom register 21 0000h cc21ic b f16ah e b5h capcom register 21 interrupt control register 0000h cc22 fe6ch 36h capcom register 22 0000h cc22ic b f16ch e b6h capcom register 22 interrupt control register 0000h cc23 fe6eh 37h capcom register 23 0000h cc23ic b f16eh e b7h capcom register 23 interrupt control register 0000h cc24 fe70h 38h capcom register 24 0000h cc24ic b f170h e b8h capcom register 24 interrupt control register 0000h cc25 fe72h 39h capcom register 25 0000h cc25ic b f172h e b9h capcom register 25 interrupt control register 0000h cc26 fe74h 3ah capcom register 26 0000h cc26ic b f174h e bah capcom register 26 interrupt control register 0000h cc27 fe76h 3bh capcom register 27 0000h table 14 : special function registers listed by name (continued) name physical address 8-bit address description reset value
st10c167 33/66 cc27ic b f176h e bbh capcom register 27 interrupt control register 0000h cc28 fe78h 3ch capcom register 28 0000h cc28ic b f178h e bch capcom register 28 interrupt control register 0000h cc29 fe7ah 3dh capcom register 29 0000h cc29ic b f184h e c2h capcom register 29 interrupt control register 0000h cc30 fe7ch 3eh capcom register 30 0000h cc30ic b f18ch e c6h capcom register 30 interrupt control register 0000h cc31 fe7eh 3fh capcom register 31 0000h cc31ic b f194h e cah capcom register 31 interrupt control register 0000h ccm0 b ff52h a9h capcom mode control register 0 0000h ccm1 b ff54h aah capcom mode control register 1 0000h ccm2 b ff56h abh capcom mode control register 2 0000h ccm3 b ff58h ach capcom mode control register 3 0000h ccm4 b ff22h 91h capcom mode control register 4 0000h ccm5 b ff24h 92h capcom mode control register 5 0000h ccm6 b ff26h 93h capcom mode control register 6 0000h ccm7 b ff28h 94h capcom mode control register 7 0000h cp fe10h 08h cpu context pointer register fc00h cric b ff6ah b5h gpt2 caprel interrupt control register 0000h csp fe08h 04h cpu code segment pointer register (read only) 0000h dp0l b f100h e 80h p0l direction control register 00h dp0h b f102h e 81h p0h direction control register 00h dp1l b f104h e 82h p1l direction control register 00h dp1h b f106h e 83h p1h direction control register 00h dp2 b ffc2h e1h port 2 direction control register 0000h dp3 b ffc6h e3h port 3 direction control register 0000h dp4 b ffcah e5h port 4 direction control register 00h dp6 b ffceh e7h port 6 direction control register 00h dp7 b ffd2h e9h port 7 direction control register 00h dp8 b ffd6h ebh port 8 direction control register 00h dpp0 fe00h 00h cpu data page pointer 0 register (10 bit) 0000h dpp1 fe02h 01h cpu data page pointer 1 register (10 bit) 0001h dpp2 fe04h 02h cpu data page pointer 2 register (10 bit) 0002h dpp3 fe06h 03h cpu data page pointer 3 register (10 bit) 0003h exicon b f1c0h e e0h external interrupt control register 0000h idchip f07ch e 3eh device identifier register 0a7h 1 idmanuf f07eh e 3fh manufacturer identifier register 0020h 1 idmem f07ah e 3dh on-chip memory identifier register 3020h 1 table 14 : special function registers listed by name (continued) name physical address 8-bit address description reset value
st10c167 34/66 idprog f078h e 3ch programming voltage identifier register 9a40h 1 mdc b ff0eh 87h cpu multiply divide control register 0000h mdh fe0ch 06h cpu multiply divide register C high word 0000h mdl fe0eh 07h cpu multiply divide register C low word 0000h odp2 b f1c2h e e1h port 2 open drain control register 0000h odp3 b f1c6h e e3h port 3 open drain control register 0000h odp6 b f1ceh e e7h port 6 open drain control register 00h odp7 b f1d2h e e9h port 7 open drain control register 00h odp8 b f1d6h e ebh port 8 open drain control register 00h ones ff1eh 8fh constant value 1s register (read only) ffffh p0l b ff00h 80h port 0 low register (lower half of port0) 00h p0h b ff02h 81h port 0 high register (upper half of port0) 00h p1l b ff04h 82h port 1 low register (lower half of port1) 00h p1h b ff06h 83h port 1 high register (upper half of port1) 00h p2 b ffc0h e0h port 2 register 0000h p3 b ffc4h e2h port 3 register 0000h p4 b ffc8h e4h port 4 register (8 bit) 00h p5 b ffa2h d1h port 5 register (read only) xxxxh p6 b ffcch e6h port 6 register (8 bit) 00h p7 b ffd0h e8h port 7 register (8 bit) 00h p8 b ffd4h eah port 8 register (8 bit) 00h pecc0 fec0h 60h pec channel 0 control register 0000h pecc1 fec2h 61h pec channel 1 control register 0000h pecc2 fec4h 62h pec channel 2 control register 0000h pecc3 fec6h 63h pec channel 3 control register 0000h pecc4 fec8h 64h pec channel 4 control register 0000h pecc5 fecah 65h pec channel 5 control register 0000h pecc6 fecch 66h pec channel 6 control register 0000h pecc7 feceh 67h pec channel 7 control register 0000h picon f1c4h e e2h port input threshold control register 0000h pp0 f038h e 1ch pwm module period register 0 0000h pp1 f03ah e 1dh pwm module period register 1 0000h pp2 f03ch e 1eh pwm module period register 2 0000h pp3 f03eh e 1fh pwm module period register 3 0000h psw b ff10h 88h cpu program status word 0000h pt0 f030h e 18h pwm module up/down counter 0 0000h pt1 f032h e 19h pwm module up/down counter 1 0000h table 14 : special function registers listed by name (continued) name physical address 8-bit address description reset value
st10c167 35/66 pt2 f034h e 1ah pwm module up/down counter 2 0000h pt3 f036h e 1bh pwm module up/down counter 3 0000h pw0 fe30h 18h pwm module pulse width register 0 0000h pw1 fe32h 19h pwm module pulse width register 1 0000h pw2 fe34h 1ah pwm module pulse width register 2 0000h pw3 fe36h 1bh pwm module pulse width register 3 0000h pwmcon0b ff30h 98h pwm module control register 0 0000h pwmcon1b ff32h 99h pwm module control register 1 0000h pwmic b f17eh e bfh pwm module interrupt control register 0000h rp0h b f108h e 84h system start-up configuration register (read only) xxh s0bg feb4h 5ah serial channel 0 baud rate generator reload register 0000h s0con b ffb0h d8h serial channel 0 control register 0000h s0eic b ff70h b8h serial channel 0 error interrupt control register 0000h s0rbuf feb2h 59h serial channel 0 receive buffer register (read only) xxh s0ric b ff6eh b7h serial channel 0 receive interrupt control register 0000h s0tbic b f19ch e ceh serial channel 0 transmit buffer interrupt control register 0000h s0tbuf feb0h 58h serial channel 0 transmit buffer register (write only) 00h s0tic b ff6ch b6h serial channel 0 transmit interrupt control register 0000h sp fe12h 09h cpu system stack pointer register fc00h sscbr f0b4h e 5ah ssc baud rate register 0000h ssccon b ffb2h d9h ssc control register 0000h ssceic b ff76h bbh ssc error interrupt control register 0000h sscrb f0b2h e 59h ssc receive buffer (read only) xxxxh sscric b ff74h bah ssc receive interrupt control register 0000h ssctb f0b0h e 58h ssc transmit buffer (write only) 0000h ssctic b ff72h b9h ssc transmit interrupt control register 0000h stkov fe14h 0ah cpu stack overflow pointer register fa00h stkun fe16h 0bh cpu stack underflow pointer register fc00h syscon b ff12h 89h cpu system configuration register 0xx0h 2 t0 fe50h 28h capcom timer 0 register 0000h t01con b ff50h a8h capcom timer 0 and timer 1 control register 0000h t0ic b ff9ch ceh capcom timer 0 interrupt control register 0000h t0rel fe54h 2ah capcom timer 0 reload register 0000h t1 fe52h 29h capcom timer 1 register 0000h t1ic b ff9eh cfh capcom timer 1 interrupt control register 0000h t1rel fe56h 2bh capcom timer 1 reload register 0000h t2 fe40h 20h gpt1 timer 2 register 0000h table 14 : special function registers listed by name (continued) name physical address 8-bit address description reset value
st10c167 36/66 notes 1. the value depends on the silicon revision and is described in the chapter xix.1. 2. the system configuration is selected during reset. 3. bit wdtr indicates a watchdog timer triggered reset. 4. the xpnic interrupt control registers control the interrupt requests from integrated x-bus peripherals. nodes where no x-peripherals are connected may be used to generate software controlled interrupt requests by setting the respective xpnir bit. t2con b ff40h a0h gpt1 timer 2 control register 0000h t2ic b ff60h b0h gpt1 timer 2 interrupt control register 0000h t3 fe42h 21h gpt1 timer 3 register 0000h t3con b ff42h a1h gpt1 timer 3 control register 0000h t3ic b ff62h b1h gpt1 timer 3 interrupt control register 0000h t4 fe44h 22h gpt1 timer 4 register 0000h t4con b ff44h a2h gpt1 timer 4 control register 0000h t4ic b ff64h b2h gpt1 timer 4 interrupt control register 0000h t5 fe46h 23h gpt2 timer 5 register 0000h t5con b ff46h a3h gpt2 timer 5 control register 0000h t5ic b ff66h b3h gpt2 timer 5 interrupt control register 0000h t6 fe48h 24h gpt2 timer 6 register 0000h t6con b ff48h a4h gpt2 timer 6 control register 0000h t6ic b ff68h b4h gpt2 timer 6 interrupt control register 0000h t7 f050h e 28h capcom timer 7 register 0000h t78con b ff20h 90h capcom timer 7 and 8 control register 0000h t7ic b f17ah e beh capcom timer 7 interrupt control register 0000h t7rel f054h e 2ah capcom timer 7 reload register 0000h t8 f052h e 29h capcom timer 8 register 0000h t8ic b f17ch e bfh capcom timer 8 interrupt control register 0000h t8rel f056h e 2bh capcom timer 8 reload register 0000h tfr b ffach d6h trap flag register 0000h wdt feaeh 57h watchdog timer register (read only) 0000h wdtcon ffaeh d7h watchdog timer control register 000xh 3 xp0ic b f186h e c3h can module interrupt control register 0000h 4 xp1ic b f18eh e c7h x-peripheral 1 interrupt control register 0000h 4 xp2ic b f196h e cbh x-peripheral 2 interrupt control register 0000h 4 xp3ic b f19eh e cfh pll unlock interrupt control register 0000h 4 zeros b ff1ch 8eh constant value 0s register (read only) 0000h table 14 : special function registers listed by name (continued) name physical address 8-bit address description reset value
st10c167 37/66 19.1 - identification registers the st10c167 has four identification registers, mapped in esfr space. these registers contain: C a manufacturer identifier, C a chip identifier, with its revision, C a internal memory and size identifier, C programming voltage description. idmanuf (f07eh / 3fh) esfr description idmanuf : manufacturer identifier - 0400h: stmicroelectronics manufacturer (jtag world- wide normalisation). idchip (f07ch / 3eh) esfr description idchip: device identifier - 0a72h for st10c167. idmem (f07ah / 3dh) esfr description idmem: 1008h for st10c167 (mcu with rom). idprog (f078h / 3ch) esfr description idprog: 0000h for st10c167 (mcu with rom).
st10c167 38/66 20 - electrical characteristics 20.1 - absolute maximum ratings note stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may affect device re- liability. during overload conditions (v in >v dd or v in st10c167 39/66 notes 1. this specification is not valid for outputs which are switched to open drain mode. in this case the respective output w ill float and the voltage results from the external circuitry. 2. the maximum current may be drawn while the respective signal line remains inactive. 3. the minimum current must be drawn in order to drive the respective signal line active. 4. this specification is only valid during reset, or during hold- or adapt-mode. port 6 pins are only affected if they are used as csx output and the open drain function is not enabled. 5. partially tested, guaranteed by design characterization. 6. the supply current is a function of the operating frequency. this dependency is illustrated in the figure below. these param eters are tested at v ddmax and 20mhz cpu clock with all outputs disconnected and all inputs at v il or v ih . 7. this parameter is tested including leakage currents. all inputs (including pins configured as inputs) at 0v to 0.1v or at v dd C 0.1v to v dd , v ref = 0v, all outputs (including pins configured as outputs) disconnected. 8. overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specifi ed range (i.e. v ov >v dd +0.5v or v ov st10c167 40/66 figure 8 : supply/idle current as a function of operating frequency 20.3.1 - a/d converter characteristics v dd = 5v 10%, v ss = 0v , t a = -40 to +125c 4.0v v aref v dd + 0.1v, v ss - 0.1v v agnd v ss + 0.2v (see table 16) notes: 1. v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 2. during the t s sample time the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within the t s sample time. after the end of the t s sample time, changes of the analog input voltage have no effect on the conversion result. values for the t sc sample clock depend on the programming. referring to the t c conversion time formula of chapter 12, to the table 9 of page 23 and to the table below: t s min = 2 t sc min = 2 t cc min = 2 x 24 x tcl = 48 tcl t s max = 2 t sc max = 2 x 8 t cc max = 2 x 8 x 96 tcl = 1536 tcl tcl is defined in section 20.4.4 at page 43. 3. the conversion time formula is: t c = 14 t cc + t s + 4 tcl (= 14tcc + 2 t sc + 4 tcl) the t c parameter includes the t s sample time, the time for determining the digital result and the time to load the result register with the result of the conversion. values for the t cc conversion clock depend on the programming. referring to the table 9 of page 23 and to the table below: t c min = 14 t cc min + t s min + 4 tcl = 14 x 24 x tcl + 48 tcl + 4 tcl = 388 tcl t c max = 14 t cc max + t s max + 4 tcl = 14 x 96 tcl + 1536 tcl + 4 tcl = 2884 tcl 4. this parameter is fixed by adc control logic. table 16 : a/d converter characteristics symbol parameter test conditions min. max. unit v ain sr analog input voltage range 1 - 8 v agnd v aref v t s cc sample time 2 - 4 48 tcl 1 536 tcl t c cc conversion time 3 - 4 388 tcl 2 884 tcl tue cc total unadjusted error 5 C 2 lsb r aref sr internal resistance of reference voltage source t cc in [ns] 6 - 7 C(t cc /165) - 0.25 k w r asrc sr internal resistance of analog source t s in [ns] 2 - 7 C(t s / 330) - 0.25 k w c ain cc adc input capacitance 7 C33pf i [ma] f cpu [mhz] 5 10 15 20 195 95 10 i cctyp i idmax i ccmax i idtyp 25
st10c167 41/66 5. tue is tested at v aref = 5.0v, v agnd = 0v, v cc = 4.9v. it is guaranteed by design characterization for all other voltages within the defined voltage range. the specified tue is guaranteed only if an overload condition (see i ov specification) occurs on maximum of 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10ma. during the reset calibration sequence the maximum tue may be 4 lsb. 6. during the conversion the adcs capacitance must be repeatedly charged or discharged. the internal resistance of the referen ce voltage source must allow the capacitance to reach its respective voltage level within t cc . the maximum internal resistance results from the programmed conversion timing. 7. partially tested, guaranteed by design characterization. 8. to remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at the adc input. the cut-off frequency of this filter must be twice the highest conversion frequency used in the application as d escribed in the formula: f cut-off = 2 / t c app where t c app is the shorter conversion time used in the application, calculated with the following formula: t c app = 14 t cc + t s + 4 tcl (= 14 t cc + 2 t sc + 4 tcl). sample time and conversion time of the st10c167s adc are programmable. the table below should be used to calculate the above timings. 20.4 - ac characteristics test waveforms adcon.15|14 (adctc) conversion clock t cc adcon.13|12 (adstc) sample clock t sc 00 tcl * 24 00 t cc 01 reserved, do not use 01 t cc * 2 10 tcl * 96 10 t cc * 4 11 tcl * 48 11 t cc * 8 figure 9 : input output waveforms figure 10 : float waveforms 2.4v 0.45v test points 0.2v dd +0.9 0.2v dd +0.9 0.2v dd -0.1 0.2v dd -0.1 ac inputs during testing are driven at 2.4v for a logic 1 and 0.4v for a logic 0. timing measurements are made at vih min for a logic 1 and vil max for a logic 0. timin g reference points v load +0.1v v load -0.1v v oh -0.1v v ol +0.1v v load v ol v oh for timing purposes a port pin is no longer floating when v load changes of 100mv. it begins to float when a 100mv change from the loaded v oh /v ol level occurs (i oh /i ol = 20ma).
st10c167 42/66 20.4.1 - definition of internal timing the internal operation of the st10c167 is controlled by the internal cpu clock f cpu . both edges of the cpu clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. the specification of the external timing (ac characteristics) therefore depends on the time between two consecutive edges of the cpu clock, called tcl periods (see figure 11). the cpu clock signal can be generated by different mechanisms. the duration of tcl periods and their variation (and also the derived external timing) depends on the mechanism used to generate f cpu . this influence must be regarded when calculating the timings for the st10c167. the example for pll operation shown in figure 11 refers to a pll factor of 4. the mechanism used to generate the cpu clock is selected during reset by the logic levels on pins p0.15-13 (p0h.7-5). 20.4.2 - clock generation modes table 18 shows the association of the combinations of these three bits with the respective clock generation mode. notes: 1. the external clock input range refers to a cpu clock range of 10...25mhz. 2. the maximum frequency depends on the duty cycle of the external clock signal. 3. the maximum input frequency is 25mhz when using an external crystal with the internal oscillator; providing that internal se rial resistance of the crystal is less than 40 w . however, higher frequencies can be applied with an external clock source on pin xtal1, but in this case, the input clock signal must reach the defined levels v il and v ih2. figure 11 : generation mechanisms for the cpu clock table 17 : cpu frequency generation p0.15-13 (p0h.7-5) cpu frequency f cpu = f xtal x f external clock input range 1 notes 111 f xtal x 4 2.5 to 6.25mhz default configuration 110 f xtal x 3 3.33 to 8.33mhz 101 f xtal x 2 5 to 12.5mhz 100 f xtal x 5 2 to 5mhz 011 f xtal x 1 1 to 25mhz direct drive 2 010 f xtal x 1.5 6.66 to 16.6mhz 001 f xtal / 2 2 to 50mhz cpu clock via prescaler 000 f xtal x 2.5 4 to 10mhz tcl tcl tcl tcl f cpu f xtal f cpu f xtal phase locked loop operation direct clock drive tcl tcl f cpu f xtal prescaler operation
st10c167 43/66 20.4.3 - prescaler operation when pins p0.15-13 (p0h.7-5) equal 001 during reset the cpu clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. the frequency of f cpu is half the frequency of f xtal and the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the period of the input clock f xtal . the timings listed in the ac characteristics that refer to tcls, therefore, can be calculated using the period of f xtal for any tcl. note that if the bit owddis in syscon register is cleared, the pll is running on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. 20.4.4 - direct drive when pins p0.15-13 (p0h.7-5) equal 011 during reset the on-chip phase locked loop is disabled and the cpu clock is directly driven from the internal oscillator with the input clock signal. the frequency of f cpu directly follows the frequency of f xtal so the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the duty cycle of the input clock f xtal . the timings listed below that refer to tcl therefore must be calculated using the minimum tcl that is possible under the respective circumstances. this minimum value can be calculated by the following formula: for two consecutive tcls the deviation caused by the duty cycle of f xtal is compensated so the duration of 2tcl is always 1/f xtal . the minimum value tcl min therefore has to be used only once for timings that require an odd number of tcls (1,3,...). timings that require an even number of tcls (2,4,...) may use the formula: note the address float timings in multiplexed bus mode (t 11 and t 45 ) use the maximum duration of tcl (tcl max = 1/f xtal x dc max ) instead of tcl min . note that if the bit owddis in syscon register is cleared, the pll is running on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. 20.4.5 - oscillator watchdog (owd) when the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the pll circuitry. this oscillator watchdog operates as follows : after a reset, the oscillator watchdog is enabled by default. to disable the owd, the bit owddis (bit 4 of syscon register) must be set. when the owd is enabled, the pll is running on its free-running frequency, and increment the oscillator watchdog counter. on each transition of xtal1 pin, the oscillator watchdog is cleared. if an external clock failure occurs, then the oscillator watchdog counter overflows (after 16 pll clock cycles). the cpu clock signal will be switched to the pll free-running clock signal, and the oscillator watchdog interrupt request (xp3int) is flagged. the cpu clock will not switch back to the external clock even if a valid external clock exits on xtal1 pin. only a hardware reset can switch the cpu clock source back to direct clock input. when the owd is disabled, the cpu clock is always fed from the oscillator input and the pll is switched off to decrease power supply current. 20.4.6 - phase locked loop for all other combinations of pins p0.15-13 (p0h.7-5) during reset the on-chip phase locked loop is enabled and provides the cpu clock (see table above). the pll multiplies the input frequency by the factor f which is selected via the combination of pins p0.15-13 (i.e. f cpu = f xtal * f). with every fth transition of f xtal the pll circuit synchronizes the cpu clock to the input clock. this synchronization is done smoothly, i.e. the cpu clock frequency does not change abruptly. due to this adaptation to the input clock the frequency of f cpu is constantly adjusted so it is locked to f xtal . the slight variation causes a jitter of f cpu which also effects the duration of individual tcls. the timings listed in the ac characteristics that refer to tcl therefore must be calculated using the minimum tcl that is possible under the respective circumstances. tcl min 1f xtal *dc min = dc duty cycle = 2tcl 1 f xtal =
st10c167 44/66 the real minimum value for tcl depends on the jitter of the pll. the pll tunes f cpu to keep it locked on f xtal . the relative deviation of tcl is the maximum when it is refered to one tcl period. it decreases according to the formula and to the figure 12 given below. for n periods of tcl the minimum value is computed using the corresponding deviation d n : where n = number of consecutive tcl periods and 1 n 40. so for a duration of 3 tcl periods (n = 3): d 3 = 4 - 3/15 = 3.8% 3tcl min = 3tcl nom x (1 - 3.8/100) = 3tcl nom x 0.962 3tcl min = (57.72ns at f cpu = 25mhz) this is especially important for bus cycles using wait states and for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baud rates, etc.) the deviation caused by the pll jitter is negligible. 20.4.7 - memory cycle variables the tables below use three variables which are derived from the busconx registers and represent the special characteristics of the programmed memory cycle. the following table describes how these variables are to be computed. tcl min tcl nom 1 d n 100 ------------- C ? ? ? ?? = d n 4n15 ) % [] C ( = figure 12 : approximated maximum pll jitter symbol description values t a ale extension tcl * t c memory cycle time wait states 2tcl * (15 - ) t f memory tristate time 2tcl * (1 - ) 32 16 8 4 2 1 2 3 4 max.jitter [%] n this approximated formula is valid for 1 n 40 and 10mhz f cpu 25mhz.
st10c167 45/66 20.4.8 - external clock drive xtal1 v dd = 5v 10%, v ss = 0v, t a = -40 to +125c unless otherwise specified. notes 1. theoretical minimum. the real minimum value depends on the duty cycle of the input clock signal. 2. 25mhz is the maximum input frequency when using an external crystal oscillator; however, 50mhz can be applied with an extern al clock source. 3. the input clock signal must reach the defined levels v il and v ih2 . symbol parameter f cpu = f xtal f cpu = f xtal / 2 f cpu = f xtal * n n = 1.5/2,/2.5/3/4/5 unit min. max. min. max. min. max. t osc sr oscillator period 40 1 1000 20 2 500 40 * n 100 * n ns t 1 sr high time 18 3 C 6 3 C 10 3 Cns t 2 sr low time 18 3 C 6 3 C 10 3 Cns t 3 sr rise time C 10 3 C 6 3 C 10 3 ns t 4 sr fall time C 10 3 C 6 3 C 10 3 ns figure 13 : external clock drive xtal1 t 1 t 3 t 4 v il t 2 t osc v ih2
st10c167 46/66 20.4.9 - multiplexed bus v dd = 5v 10%, v ss = 0v, t a = -40 to +125c c l (for port0, port1, port 4, ale, rd , wr , bhe , clkout) = 100pf, c l (for port 6, cs ) = 100pf ale cycle time = 6 tcl + 2t a + t c + t f (120ns at 25mhz cpu clock without wait states) table 18 : multiplexed bus characteristics symbol parameter max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. t 5 cc ale high time 10 + t a C tcl - 10 + t a Cns t 6 cc address setup to ale 4 + t a C tcl - 16+ t a Cns t 7 cc address hold after ale 10 + t a C tcl - 10 + t a Cns t 8 cc ale falling edge to rd , wr (with rw-delay) 10 + t a C tcl - 10 + t a Cns t 9 cc ale falling edge to rd , wr (no rw-delay) -10 + t a C -10 + t a Cns t 10 1 cc address float after rd , wr (with rw-delay) C6 C 6ns t 11 1 cc address float after rd , wr (no rw-delay) C 26 C tcl + 6 ns t 12 cc rd , wr low time (with rw-delay) 30 + t c C 2tcl - 10 + t c Cns t 13 cc rd , wr low time (no rw-delay) 50 + t c C 3tcl - 10 + t c Cns t 14 sr rd to valid data in (with rw-delay) C 20 + t c C 2tcl - 20+ t c ns t 15 sr rd to valid data in (no rw-delay) C 40 + t c C 3tcl - 20+ t c ns t 16 sr ale low to valid data in C 40 + t a + t c C 3tcl - 20 + t a + t c ns t 17 sr address/unlatched cs to valid data in C 50 + 2t a + t c C 4tcl - 30 + 2t a + t c ns t 18 sr data hold after rd rising edge 0 C 0 C ns t 19 1 sr data float after rd C 26 + t f C 2tcl - 14 + t f ns t 22 cc data valid to wr 20 + t c C 2tcl - 20 + t c Cns t 23 cc data hold after wr 26 + t f C 2tcl - 14 + t f Cns t 25 cc ale rising edge after rd , wr 26 + t f C 2tcl - 14 + t f Cns t 27 cc address/unlatched cs hold after rd , wr 26 + t f C 2tcl - 14 + t f Cns t 38 cc ale falling edge to latched cs -4 - t a 10 - t a -4 - t a 10 - t a ns t 39 sr latched cs low to valid data in C 40 + t c + 2t a C 3tcl - 20 + t c + 2t a ns t 40 cc latched cs hold after rd , wr 46 + t f C 3tcl - 14 + t f Cns
st10c167 47/66 note 1. guaranteed by design characterization. t 42 cc ale fall. edge to rdcs , wrcs (with rw delay) 16 + t a C tcl - 4 + t a Cns t 43 cc ale fall. edge to rdcs , wrcs (no rw delay) -4 + t a C-4 + t a Cns t 44 1 cc address float after rdcs , wrcs (with rw delay) C0 C 0ns t 45 1 cc address float after rdcs , wrcs (no rw delay) C 20 C tcl ns t 46 sr rdcs to valid data in (with rw delay) C 16 + t c C 2tcl - 24 + t c ns t 47 sr rdcs to valid data in (no rw delay) C 36 + t c C 3tcl - 24 + t c ns t 48 cc rdcs , wrcs low time (with rw delay) 30 + t c C 2tcl - 10 + t c Cns t 49 cc rdcs , wrcs low time (no rw delay) 50 + t c C 3tcl - 10 + t c Cns t 50 cc data valid to wrcs 26 + t c C 2tcl - 14+ t c Cns t 51 sr data hold after rdcs 0C 0 Cns t 52 1 sr data float after rdcs C 20 + t f C 2tcl - 20 + t f ns t 54 cc address hold after rdcs , wrcs 20 + t f C 2tcl - 20 + t f Cns t 56 cc data hold after wrcs 20 + t f C 2tcl - 20 + t f Cns table 18 : multiplexed bus characteristics (continued) symbol parameter max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max.
st10c167 48/66 figure 14 : external memory cycle : multiplexed bus, with/without read/write delay, normal ale data in data out address address t 38 t 10 read cycle write cycle t 5 t 16 t 39 t 40 t 25 t 27 t 18 t 14 t 22 t 23 t 12 t 8 t 8 t 6m t 19 address t 17 t 6 t 7 t 9 t 11 t 13 t 15 t 16 t 12 t 13 address t 9 t 17 t 6 t 27 clkout ale csx a23-a16 (a15-a8) bus (p0) rd bus (p0) wr wrl bhe wrh
st10c167 49/66 figure 15 : external memory cycle: multiplexed bus, with/without read/write delay, extended ale data out address data in address address t 5 t 16 t 6 t 7 t 39 t 40 t 14 t 8 t 18 t 23 t 6 t 27 t 38 t 10 t 19 t 25 t 17 t 9 t 11 t 15 t 12 t 13 t 8 t 10 t 9 t 11 t 12 t 13 t 22 t 27 t 17 t 6 read cycle write cycle clkout ale csx a23-a16 (a15-a8) bus (p0) rd bus (p0) wr wrl bhe wrh
st10c167 50/66 figure 16 : external memory cycle: multiplexed bus, with/without read/write delay, normal ale, read/ write chip select read cycle write cycle clkout ale a23-a16 (a15-a8) bus (p0) bus (p0) bhe data in data out address address t 44 t 5 t 16 t 25 t 27 t 51 t 46 t 50 t 56 t 48 t 42 t 42 t 6 t 52 address t 17 t 6 t 7 t 43 t 45 t 49 t 47 t 16 t 48 t 49 address t 43 rdcsx wrcsx
st10c167 51/66 figure 17 : external memory cycle: multiplexed bus, with/without read/write delay, extended ale, read/ write chip select data out address data in address address t 5 t 16 t 6 t 7 t 46 t 42 t 42 t 50 t 18 t 56 t 6 t 54 t 44 t 19 t 25 t 17 t 43 t 45 t 47 t 48 t 49 t 49 t 43 t 48 t 44 t 45 read cycle write cycle clkout ale a23-a16 (a15-a8) bus (p0) bus (p0) bhe rdcsx wrcsx
st10c167 52/66 20.4.10 - demultiplexed bus v dd = 5v 10%, v ss = 0v, t a = -40 to +125c c l (for port0, port1, port 4, ale, rd , wr , bhe , clkout) = 100pf, c l (for port 6, cs ) = 100pf ale cycle time = 4 tcl + 2t a + t c + t f (80ns at 25mhz cpu clock without wait states) table 19 : demultiplexed bus characteristics symbol parameter max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. t 5 cc ale high time 10 + t a C tcl - 10+ t a Cns t 6 cc address setup to ale 4 + t a C tcl - 16+ t a Cns t 8 cc ale falling edge to rd , wr (with rw-delay) 10 + t a C tcl - 10 + t a Cns t 9 cc ale falling edge to rd , wr (no rw-delay) -10 + t a C -10 + t a Cns t 12 cc rd , wr low time (with rw-delay) 30 + t c C 2tcl - 10 + t c Cns t 13 cc rd , wr low time (no rw-delay) 50 + t c C 3tcl - 10 + t c Cns t 14 sr rd to valid data in (with rw-delay) C 20 + t c C 2tcl - 20 + t c ns t 15 sr rd to valid data in (no rw-delay) C 40 + t c C 3tcl - 20 + t c ns t 16 sr ale low to valid data in C 40 + t a + t c C 3tcl - 20 + t a + t c ns t 17 sr address/unlatched cs to valid data in C50 + 2t a + t c C 4tcl - 30 + 2t a + t c ns t 18 sr data hold after rd rising edge 0 C 0 C ns t 20 1 sr data float after rd rising edge (with rw-delay 1 ) C 26 + t f C 2tcl - 14 + t f + 2t a 2 ns t 21 1 sr data float after rd rising edge (no rw-delay 1 ) C 10 + t f C tcl - 10 + t f + 2t a 2 ns t 22 cc data valid to wr 20 + t c C 2tcl- 20 + t c Cns t 24 cc data hold after wr 10 + t f C tcl - 10+ t f Cns t 26 cc ale rising edge after rd , wr -10 + t f C -10 + t f Cns t 28 cc address/unlatched cs hold after rd , wr 2 0 + t f C0 + t f Cns t 38 cc ale falling edge to latched cs -4 - t a 10 - t a -4 - t a 10 - t a ns t 39 sr latched cs low to valid data in C 40 + t c + 2t a C 3tcl - 20 + t c + 2t a ns t 41 cc latched cs hold after rd , wr 6 + t f C tcl - 14 + t f Cns t 42 cc ale falling edge to rdcs , wrcs (with rw-delay) 16 + t a C tcl - 4 + t a Cns
st10c167 53/66 notes 1. guaranteed by design characterization. 2. rw-delay and ta refer to the next following bus cycle. 3. read data is latched with the same clock edge that triggers the address change and the rising rd edge. therefore address changes before the end of rd have no impact on read cycles. t 43 cc ale falling edge to rdcs , wrcs (no rw-delay) -4 + t a C-4 + t a Cns t 46 sr rdcs to valid data in (with rw-delay) C16 + t c C 2tcl - 24 + t c ns t 47 sr rdcs to valid data in (no rw-delay) C36 + t c C 3tcl - 24 + t c ns t 48 cc rdcs , wrcs low time (with rw-delay) 30 + t c C 2tcl - 10 + t c Cns t 49 cc rdcs , wrcs low time (no rw-delay) 50 + t c C 3tcl - 10 + t c Cns t 50 cc data valid to wrcs 26 + t c C 2tcl - 14 + t c Cns t 51 sr data hold after rdcs 0C 0 Cns t 53 1 sr data float after rdcs (with rw-delay) C 20 + t f C 2tcl - 20 + t f ns t 68 1 sr data float after rdcs (no rw-delay) C0 + t f C tcl - 20 + t f ns t 55 cc address hold after rdcs , wrcs -10 + t f C -10 + t f Cns t 57 cc data hold after wrcs 6 + t f C tcl - 14 + t f Cns table 19 : demultiplexed bus characteristics (continued) symbol parameter max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max.
st10c167 54/66 figure 18 : external memory cycle: demultiplexed bus, with/without read/write delay, normal ale write cycle clkout ale a23-a16 (a15-a8) data bus (p0) bhe wr wrl wrh data in data out t 38 t 5 t 16 t 39 t 41 t 18 t 14 t 22 t 12 address t 17 t 13 t 15 t 12 t 13 t 21 t 20 t 81 t 80 t 26 t 24 t 17 t 6 t 41u t 6 t 80 t 81 t 28 csx read cycle data bus (p0) rd
st10c167 55/66 figure 19 : external memory cycle: demultiplexed bus, with/without read/write delay, extended ale address t 5 t 16 t 39 t 41 t 14 t 24 t 6 t 38 t 20 t 26 t 17 t 15 t 12 t 13 t 12 t 13 t 22 data in t 18 t 21 t 6 t 17 t 28 t 28 data out t 80 t 81 t 80 t 81 read cycle write cycle clkout ale csx a23-a16 (a15-a8) data bus rd data bus wr wrl bhe wrh (p0) (p0)
st10c167 56/66 figure 20 : external memory cycle: demultiplexed bus, with/without read/write delay, normal ale, read/ write chip select read cycle write cycle clkout ale a23-a16 (a15-a8) data bus (p0) bhe data in data out t 5 t 16 t 51 t 46 t 50 t 48 address t 17 t 49 t 47 t 48 t 49 t 68 t 53 t 83 t 82 t 26 t 57 t 55 t 6 t 82 t 83 rdcsx data bus (p0) wrcsx
st10c167 57/66 figure 21 : external memory cycle: demultiplexed bus, with/without read/write delay, extended ale, read/write chip select address t 5 t 16 t 46 t 57 t 6 t 53 t 26 t 17 t 47 t 48 t 49 t 48 t 49 t 50 data in t 51 t 68 t 55 data out t 82 t 83 t 82 t 83 read cycle write cycle clkout ale a23-a16 (a15-a8) data bus (p0) bhe rdcsx data bus (p0) wrcsx
st10c167 58/66 20.4.11 - clkout and ready v dd = 5v 10%, v ss = 0v, t a = -40 to +125c c l (for port0, port1, port 4, ale, rd , wr , bhe , clkout) = 100pf c l (for port 6, cs ) = 100pf notes 1.these timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. demultiplexed bus is the worst case. for multiplexed bus 2tcl are to be added to the maximum values. this adds even more tim e for deactivating ready. the 2t a and t c refer to the next following bus cycle, t f refers to the current bus cycle. table 20 : clkout and ready characteristics symbol parameter max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. t 29 cc clkout cycle time 40 40 2tcl 2tcl ns t 30 cc clkout high time 14 C tcl C 6 C ns t 31 cc clkout low time 10 C tcl C 10 C ns t 32 cc clkout rise time C 4 C 4 ns t 33 cc clkout fall time C 4 C 4 ns t 34 cc clkout rising edge to ale falling edge 0 + t a 10 + t a 0 + t a 10 + t a ns t 35 sr synchronous ready setup time to clkout 14 C 14 C ns t 36 sr synchronous ready hold time after clkout 4C 4 C ns t 37 sr asynchronous ready low time 54 C 2tcl + 14 C ns t 58 sr asynchronous ready setup time 1 14 C 14 C ns t 59 sr asynchronous ready hold time 1 4C 4 C ns t 60 sr async. ready hold time after rd , wr high (demultiplexed bus) 2 0 0 + 2t a + t c + t f 2 0 tcl - 20 + 2t a + t c + t f 2 ns
st10c167 59/66 figure 22 : clkout and ready notes 1. cycle as programmed, including mctc waitstates (example shows 0 mctc ws). 2. the leading edge of the respective command depends on rw-delay. 3. ready sampled high at this sampling point generates a ready controlled wait state, ready sampled low at this sampling point terminates the currently running bus cycle. 4. ready may be deactivated in response to the trailing (rising) edge of the corresponding command (rd or wr ). 5. if the asynchronous ready signal does not fulfill the indicated setup and hold times with respect to clkout (e.g. because clkout is not enabled), it must fulf ill t 37 in order to be safely synchronized. this is guaranteed, if ready is removed in response to the command (see note 4)). 6. multiplexed bus modes have a mux waitstate added after a bus cycle, and an additional mttc waitstate may be inserted here. for a multiplexed bus with mttc waitstate this delay is 2 clkout cycles, for a demultiplexed bus without mttc waitstate this de lay is zero. 7. the next external bus cycle may start here. clkout ale t 30 t 34 sync ready t 35 t 36 t 35 t 36 async ready t 58 t 59 t 58 t 59 waitstate ready mux/tristate 6) t 32 t 33 t 29 running cycle 1) t 31 t 37 3) 3) 5) command rd, wr t 60 4) 6) 2) 7) 3) 3)
st10c167 60/66 20.4.12 - external bus arbitration v dd = 5v 10%, v ss = 0v, t a = -40 to +125c c l (for port0, port1, port 4, ale, rd , wr , bhe , clkout) = 100pf c l (for port 6, cs ) = 100pf note 1. guaranteed by design characterization. notes 1. the st10c167 will complete the currently running bus cycle before granting bus access. 2. this is the first possibility for breq to become active. 3. the cs outputs will be resistive high (pullup) after t 64 . table 21 : external bus arbitration symbol parameter max. cpu clock = 25mhz variable cpu clock 1/2tcl = 1 to 25mhz unit min. max. min. max. t 61 sr hold input setup time to clkout 20 C 20 C ns t 62 cc clkout to hlda hig or breq low delay C 20 C 20 ns t 63 cc clkout to hlda low or breq high delay C 20 C 20 ns t 64 cc csx release C 1 20C20ns t 65 cc csx drive -424-424ns t 66 cc other signals release C 1 20C20ns t 67 cc other signals drive -4 24 -4 24 ns figure 23 : external bus arbitration, releasing the bus clkout hold t 61 hlda t 63 other signals t 66 1) csx (on p6.x) t 64 1) 2) breq t 62 3)
st10c167 61/66 figure 24 : external bus arbitration, (regaining the bus) notes 1. this is the last opportunity for breq to trigger the indicated regain-sequence. even if breq is activated earlier, the regain-sequence is initiated by hold going high. please note that hold may also be deactivated without the st10c167 requesting the bus. 2. the next st10c167 driven bus cycle may start here. 20.4.13 - high-speed synchronous serial interface (ssc) timing master mode v cc = 5v 10%, v ss = 0v, cpu clock = 25mhz, t a = -40 to +125c, c l = 100pf note 1. timing guaranteed by design. symbol parameter max. baud rate = 6.25m baud ( = 0001h) variable baud rate (=0001h-ffffh) unit min. max. min. max. t 300 cc ssc clock cycle time 160 160 8 tcl 262144 tcl ns t 301 cc ssc clock high time 70 C t 300 /2 - 10 Cns t 302 cc ssc clock low time 70 C t 300 /2 - 10 Cns t 303 cc ssc clock rise time C 10 C 10 ns t 304 cc ssc clock fall time C 10 C 10 ns t 305 cc write data valid after shift edge C 15 C 15 ns t 306 1 cc write data hold after shift edge -2 C -2 C ns t 307p sr read data setup time before latch edge, phase error detection on (sscpen = 1) 60 C 2tcl+20 C ns t 308p sr read data hold time after latch edge, phase error detection on (sscpen = 1) 4tcl C 4tcl C ns t 307 sr read data setup time before latch edge, phase error detection off (sscpen = 0) 40 C 40 C ns t 308 sr read data hold time after latch edge, phase error detection off (sscpen = 0) 0C0Cns clkout hold hlda other signals t 62 csx (on p6.x) t 67 t 62 1) 2) t 65 t 61 breq t 63 t 62
st10c167 62/66 the formula for ssc clock cycle time is : t 300 = 4 tcl * ( + 1) where represents the content of the ssc baud rate register, taken as unsigned 16-bit integer. notes 1. the phase and polarity of shift and latch edge of sclk is programmable. this figure uses the leading clock edge as shif t edge (drawn in bold), with latch on trailing edge (sscph = 0b), idle clock line is low, leading clock edge is low-to-high transition (sscpo = 0b). 2. the bit timing is repeated for all bits to be transmitted or received. slave mode v cc = 5v 10%, v ss = 0v, cpu clock = 25mhz, t a = -40 to +125c, c l = 100pf note 1. timing guaranteed by design. figure 25 : ssc master timing symbol parameter max baud rate=6.25mbd ( = 0001h) variable baud rate (=0001h-ffffh) unit min. max. min. max. t 310 sr ssc clock cycle time 160 160 8 tcl 262144 tcl ns t 311 sr ssc clock high time 70 C t 310 /2 - 10 Cns t 312 sr ssc clock low time 70 C t 310 /2 - 10 Cns t 313 sr ssc clock rise time C 10 C 10 ns t 314 sr ssc clock fall time C 10 C 10 ns t 315 cc write data valid after shift edge C 54 C 2 tcl + 14 ns t 316 cc write data hold after shift edge 0 C 0 C ns t 317p sr read data setup time before latch edge, phase error detection on (sscpen = 1) 100 C 4tcl + 20 C ns t 318p sr read data hold time after latch edge, phase error detection on (sscpen = 1) 140 C 6tcl + 20 C ns t 317 sr read data setup time before latch edge, phase error detection off (sscpen = 0) 10 C 10 C ns t 318 sr read data hold time after latch edge, phase error detection off (sscpen = 0) 0C 0 Cns t 303 t 304 t 305 t 305 t 305 t 306 1st out bit last out bit 2nd out bit t 300 t 302 t 301 1) 2) t 307 2nd.in bit 1st.in bit t 308 t 307 last.in bit t 308 sclk mtsr mrst
st10c167 63/66 the formula for ssc clock cycle time is: t 310 = 4 tcl * ( + 1) where represents the content of the ssc baud rate register, taken as unsigned 16-bit integer. notes 1. the phase and polarity of shift and latch edge of sclk is programmable. this figure uses the leading clock edge as shif t edge (drawn in bold), with latch on trailing edge (sscph = 0b), idle clock line is low, leading clock edge is low-to-high transition (sscpo = 0b). 2. the bit timing is repeated for all bits to be transmitted or received. figure 26 : ssc slave timing t 313 t 314 t 315 t 315 t 315 t 316 1st out bit last out bit 2nd out bit t 310 t 312 t 311 1) 2) t 317 2nd.in bit 1st.in bit t 318 t 317 last.in bit t 318 sclk mrst mtsr
st10c167 64/66 21 - package mechanical data note 1. package dimensions are in mm. the dimensions quoted in inches are rounded. figure 27 : package outline pqfp144 (28 x 28mm) dimensions millimeters 1 inches (approx) minimum typical maximum minimum typical maximum a 4.07 0.160 a1 0.25 0.010 a2 3.17 3.42 3.67 0.125 0.133 0.144 b 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 d 30.95 31.20 31.45 1.219 1.228 1.238 d1 27.90 28.00 28.10 1.098 1.102 1.106 d3 22.75 0.896 e 0.65 0.026 e 30.95 31.20 31.45 1.219 1.228 1.238 e1 27.90 28.00 28.10 1.098 1.102 1.106 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k 0 (min.), 7 (max.) 144 109 d3 e 37 72 1 36 b a1 a2 a d1 d 73 108 e3 e1 e 0,10 mm .004 inch seating plane c l k l1
st10c167 65/66 22 - ordering information note xx : rom code identification characters salestype temperature range package st10c167-q3/xx 1 -40c to 125c pqfp144 (28 x 28mm) st10c167-q6/xx 1 -40c to 85c pqfp144 (28 x 28mm)
st10c167 66/66 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states http://www.st.com st10c167.ref

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